1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a Thin-Film Transistor (TFT) with the Lightly-Doped Offset (LDO) structure and a memory cell for a Static Random Access Memory (SRAM).
2. Description of the Prior Art
TFTs have been popularly used in the Liquid-Crystal Displays (LCDs) in which semiconductor circuits using the TFTs are formed on a glass substrate and the memory cell of SRAMs in which p-channel TFTs are used as load elements. The TFTs used in the LCDs are mainly formed by amorphous silicon and those used in the SRAMs are mainly formed by polycrystalline silicon (i.e., polysilicon). This material difference is due to the thermal process difference included in their fabrication sequences and the necessity of a high carrier mobility for the TFTs used in the SRAMs.
With the memory cell of the SRAMs, from the viewpoint of higher integration, it was advantageous that the load device is formed by a high resistance element. However, in recent years, the problems relating to leakage currents, noises, and .alpha.-ray-induced soft errors have been becoming obvious as the power supply voltage has been lowering with the progressing miniaturization. Thus, the configuration where a p-channel TFT is used as the load element of a memory cell of an SRAM has been becoming an important matter.
FIG. 19 shows a typical circuit configuration of a memory cell of an SRAM, in which six Metal-Oxide-Semiconductor (MOS) transistors are used.
As shown in FIG. 19, this memory cell is comprised of two n-channel access MOS transistors TA1 and TA2, two n-channel driver MOS transistors TD1 and TD2, and two p-channel load MOS transistors TL1 and TL2. The transistors TD1 and TL1 constitute a first inverter and the transistors TD2 and TL2 constitute a second inverter. The first and second inverters are cross-coupled at two nodes N1 and N2.
Source regions of the transistors TD1 and TD2 are connected to a ground line GND. Source regions of the transistors TL1 and TL2 are connected to a power supply line V.sub.DD. One of a pair of source/drain regions of the transistor TA1 and one of a pair of source/drain regions of the transistor TA2 are connected to a pair of bit lines BL1 and BL2, respectively. Another of the pair of source/drain regions of the transistor TA1 and another of the pair of source/drain regions of the transistor TA2 are connected to the nodes N1 and N2, respectively. Gate electrodes of the transistors TL1 and TL2 are connected to a common word line WL. The signals to be applied to the pair of bit lines BL1 and BL2 are opposite in phases.
When the electric potential at the node N1 is in a high level and the that at the node N2 is in a low level, the load transistor TL1 is in the ON (i.e., conductive) state and the load transistor TL2 is in the OFF (i.e., non-conductive) state. If the potential at the node N1 is temporarily lowered due to a leakage current, a noise, or an .alpha.-ray-induced electric charge, the ON-state of the transistor TL1 is strengthened to thereby supply electric charges to the node N1, recovering the potential lowering at the node N1.
The load transistors TL1 and TL2 have by far higher capabilities for supplying the electric charges to the nodes N1 and N2 than that of the high-resistance load element Therefore, the information or data value stored in the memory cell is difficult to be inverted. This lead to high stability of the memory cell.
The stand-by current of the SRAM is dependent upon the current flowing through the load transistor TL2 in the OFF state and the bit number.
If a p-channel TFT is used as the p-channel load transistor TL1 or TL2, this TFT needs to have both of a high current-driving capability (i.e., high ON current) and a low stand-by current (i.e., low OFF current). The high ON-current makes it possible to quickly raise the low node potential immediately after the data writing operation up to the power supply voltage, which is advantageous for high-speed operation.
To satisfy this requirement, the inventor and others reported an improved p-channel TFT having the Lightly-Doped Offset (LDO) structure, which was disclosed in Proceedings of 1991 Japan Applied Physics Society Spring Lecture-Meeting, p. 671, Lecture No. 30p-T-2, published in 1991. This p-channel TFT with the LDO structure is fabricated in the following way.
First, as shown in FIG. 1A, an insulating film 402 with a thickness of 100 to 800 nm is formed on a semiconductor substrate 401 by thermal oxidation or Chemical Vapor Deposition (CVD). The insulating film 402 is made of an oxide. After a gate electrode 404 with a thickness of 50 to 100 nm is formed on the insulating film 402, a gate insulating film 406, which is made of silicon dioxide and has a thickness of 5 to 20 nm, is formed on the insulating film 402 over the entire substrate 401 by Low-Pressure CVD (LPCVD). The gate electrode 404 is covered with the gate insulating film 406.
Further, an undoped polysilicon film (not shown) is formed on the gate insulating film 406 over the whole substrate by LPCVD. An n-type impurity such as phosphorus (P) is doped into this polysilicon film by ion-implantation until this polysilicon film has a doping concentration of 1.times.10.sup.15 to 1.times.10.sup.18 atoms/cm.sup.3. The impurity-doped polysilicon film is patterned to thereby form a patterned n.sup.- -type polysilicon film 411. The state at this stage is shown in FIG. 1A.
Subsequently, as shown in FIG. 1B, using a patterned photoresist film 426a as a mask, boron (as a p-type dopant) is selectively doped into the n.sup.- -type polysilicon film 411 by ion-implantation so that the implanted part of the n.sup.- -type polysilicon film 411 has a doping concentration of 1.times.10.sup.18 to 1.times.10.sup.19 atoms/cm.sup.3. Thus, a p.sup.- -type polysilicon region 415 is formed in the n.sup.- -type polysilicon film 411. The remaining part of the n.sup.- -type polysilicon film 411 serves as an n.sup.- -type polysilicon region 411a. The state at this stage is shown in FIG. 1B.
After the photoresist film 426a is then removed, as shown in FIG. 1C, using a patterned photoresist film 426b as a mask, boron (as a p-type dopant) is selectively doped into the p.sup.- -type polysilicon region 415 and the n.sup.- -type polysilicon region 411a. Thus, a p.sup.+ -type polysilicon region 416a is formed in the p.sup.- -type polysilicon region 415 and another p.sup.+ -type polysilicon region 416b is formed in the n.sup.- -type polysilicon region 411a. The p.sup.+ -type polysilicon regions 416a and 416b have doping concentrations of 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3. The remaining part of the n.sup.- -type polysilicon region 411a serves as an n.sup.- -type polysilicon region 411aa. The state at this stage is shown in FIG. 1C.
Then, the photoresist film 426b is removed. Thus, the above-described p-channel TFT with the LDO structure is completed, as shown in FIG. 1D.
Following this, although not shown, an interlayer insulating film and a metallic wiring film are successively formed on the TFT by know processes.
This p-channel TFT with the LDO structure is of the bottom gate type. The p.sup.+ -type polysilicon region 416b, the n.sup.- -type polysilicon region 411a, and the p.sup.+ -type polysilicon region 416a serve as a source region, a channel region, and a drain region, respectively. The p.sup.+ -type polysilicon region 416a serving as the drain region is laterally shifted toward the right-hand side in FIG. 1D with respect to the gate electrode 404 by 0.1 to 0.6 .mu.m. In other words, the drain region 416a has an offset of 0.1 to 0.6 .mu.m with respect to the gate electrode 404. The p.sup.- -type polysilicon region 415a, which is located between the n.sup.- -type channel region 411aa and the p.sup.+ -type drain region 416a, constitute an offset region.
The p.sup.- -type polysilicon offset region 415a has an effect of decreasing the gradient of the dopant concentration between the n.sup.- -type channel region 411aa and the p.sup.+ -type drain region 416a. Not only the positional shift of the drain region 416a but also this gradient-decreasing effect will relax the electric field near the drain region 416a. Therefore, the OFF current of the p-channel TFT with the LDO structure is readily decreased to a low level compared with the simple offset structure where the offset region is formed by a same semiconductor as that of the channel region.
Further, since the p.sup.+ -type drain region 416a serves as the drain region, the parasitic resistance in the drain region is decreased. Thus, the ON current of the TFT with the LDO structure is readily increased compared with the simple offset structure.
The LDO structure may be applied to TFTs of the top gate type. Also, if the gate insulating film needs to have a sufficiently large thickness, a patterned p.sup.- -type polysilicon film having a lower doping concentration than the p.sup.- -type polysilicon film 415a may be used instead of the patterned n.sup.- -type polysilicon film 411.
Moreover, the LDO structure may be applied to the TFTs designed for LCDs where an amorphous polysilicon is mainly used for fabricating the TFTs. The LDO structure may be applied to n-channel TFTs.
As described above, with the conventional p-channel TFT with the LDO structure shown in FIG. 1D, the p.sup.- -type polysilicon region 415a located between the n.sup.- -type polysilicon channel region 411aa and the p.sup.+ -type polysilicon drain region 416a serves as the offset region. Due to the existence of the p.sup.- -type polysilicon offset region 415a, the ON current of the TFT with the LDO structure is greater in absolute value than that with the simple offset structure, and the OFF current of the TFT with the LDO structure is less in absolute value than that with the simple offset structure.
However, the conventional TFT with the LDO structure has the following problem.
The p.sup.- -type polysilicon offset region 415a needs to have a specific "offset length" allowing the Off current to decrease to a desired level, where the offset length is defined as the length from the drain-side edge of the n.sup.- -type channel region 411aa to the channel-side edge of the p.sup.+ -type drain region 416a. The p.sup.- -type polysilicon offset region 415a serves as a resistor serially-connected to the n.sup.- -type channel region 411aa and the p.sup.+ -type drain region 416a, which decreases the ON current. The resistance of this resistor varies as a function of the doping concentration of the p.sup.- -type polysilicon offset region 415a and the offset length. Therefore, if the doping concentration of the p.sup.- -type polysilicon offset region 415a is increased, the resistance of the resistor may be decreased. In this case, however, there arises a disadvantage that the OFF current is increased due to the electric-field increase near the channel-side edge of the drain region 416a.
Thus, with the conventional p-channel TFT with the LDO structure, the ON and OFF currents constitute an antinomy.
A similar antinomy exists in a memory cell of an SRAM using the conventional p-channel TFT with the LDO structure.
Specifically, if the length of the p.sup.- -type polysilicon offset region 415a (i.e., the offset length) is shortened and the doping concentration of the offset region 415a is raised, the ON current of the TFT will be increased. This enables the high-speed operation of the SRAM and stabilizes the operation of the TFT at a low power supply voltage. However, in this case, the stand-by current of the TFT is raised due to the increased ON current and as a result, it is difficult to reduce the electric power dissipation of the SRAM.
Also, the offset-length tends to fluctuate for the two p-channel TFTs in the memory cell during the photolithography process in the fabrication process sequence. Therefore, the operation of the memory cell tends to be unstable at a low power-supply voltage due to this offset-length fluctuation.